Verification engineer job description

Verification Engineer

What is a verification engineer / design verification engineer? Discover it with our job description: roles & responsibilities, educational background, skills,…

Are you looking for a company specializing in FPGA/ASIC/SoC design verification to assist you in your project?
Read more about our digital design verification services and our analog mixed signal verification services.
Then do not hesitate to contact us, so that we can discuss about it together.

ELSYS is an ARM Approved Design Partner, a Microchip Authorized Design Partner and is member of the Xilinx Alliance Program. We have design centers in Europe (France), Eastern Europe (Serbia) and a branch in the USA (California, in the Silicon Valley).


What does a verification engineer do: Roles & Responsibilities

The verification engineer operates before the FPGA, ASIC or SoC production phase. He works with the design teams (FPGA engineers, microelectronic engineers, etc.) in order to verify their designs (IP, sub-system, system).

The verification can be realized at different abstraction levels.

RTL unit blocks verification

The verification can be made at the RTL blocks level. Thus, we test all the functionalities of an IP through simulations.

Verification at the sub-system level

The verification can also be realized at the sub-system level including several IP. Then, we check all their functionalities and their integration in the sub-system.

Top level verification

Once the RTL design is verified at the unit level, we can integrate it at the top level.

These unit verifications, sub-system or top level, are made:

  • With deterministic tests with references comparisons (golden reference, VHDL,…) that allow knowing if the test succeeds or fails (PASS or FAIL).
  • By random vectors covering a maximum number of scenarios. For example, we use the SystemVerilog (UVM) advanced methodology with random, constraints, functional coverage,…

Formal verification

The formal verification consists in testing the operation of the integrated circuit at a modelled mathematics level (for example by using the FormalPro tool), there is no associated simulation.

This way, for all or some of these abstraction levels, the verification engineer has to set some test plans and the covering points, to set the environment of the tests (injector and checkers), to write the tests, to launch them and to analyse the results.

This last analysing step is critical. Indeed, one has to define the criteria that will allow to judge if a design is conform to the specification or, at the contrary, to estimate the risks associated in case of use.

These analysis reports are ideally made in an automated way (TCL scripts, Perl, etc.).

Finally, once the problems are known and described, the verification engineers can help the developer to resolve them by doing some « reverse engineering ». However, these tasks are restricted to experienced engineers who have experience in integrated circuit design.

What is the difference between verification and validation?

The verification appears before the production phase of an integrated circuit, whereas the validation takes place after.

The experienced verification engineer may help his validation engineers colleagues for example by reproducing the problems faced at the RTL code level.

How to become a verification engineer?

Having experience in microelectronic or FPGA is not mandatory but it could be a plus: this way the engineer has a better understanding of the IP, the sub-system and system and facilitates the resolution of the problems discovered.

Required skills

The verification engineer has many skills and uses specific tools:

  • Skills in ASIC / FPGA verification (directed test or SystemVerilog / UVM)
  • Basic knowledge in design techniques Verilog or VHDL
  • A good knowledge of simulation flow
  • Good basis in scripting Python, Perl, Bash…
  • For non-native English speakers, a good level in English, both writing and oral skills

Humanly, you have to be rigorous and have a good analytical mind, you have to enjoy working in a team and being diplomatic, in particular when you have to point out the bugs discovered.

Verification engineer salary

For a young graduate, in France, it starts generally between 33K and 36K€.


ELSYS Design recruits verification engineers in France for its design centers located in Paris, Rennes, Nantes, Grenoble, Lyon, Nice Sophia Antipolis, Aix-en-Provence and Toulouse. You can view the offers on our jobs board, or submit a spontaneous application.
ELSYS Eastern Europe, our subsidiary in Serbia, also proposes jobs for verification engineers.

You may also be interested in our UVM verification engineer job description, UVM standing for Universal Verification Methodology.