Here is a typical FPGA internship offer for students in their final year of engineering school or master’s degree: tasks, desired profile, skills, duration, reward and location.
To apply, go to our job site.
If there are no offers available at the time you consult the ads, please do not hesitate to submit an unsolicited application.
- Description of the internship
- Required profile
- Location of the internship
FPGA INTERNSHIP DESCRIPTION
The internship consists of leading an FPGA design project from A to Z, like a real engineer.
Starting from a fixed objective, the trainee must:
- Analyze the need and feasibility.
- Write the specifications.
- Design the architecture of the FPGA.
- Code in VHDL.
- Carry out the various stages of unit testing, integration and validation.
- Write the associated documentation.
Through this internship, which is both stimulating and professionalizing, our objective is to make our future interns operational engineers with a taste for quality work.
To achieve this objective, we set up a high level of technical training with passionate, motivated and pedagogical tutors.
We also pay particular attention to the respect of industrial constraints such as:
- Processes (architecture, technical specifications, test and integration specifications, peer review, schedule management…)
- The quality of the code (readability, robustness & maintainability)
You are in last year of engineering school, or 2nd year of a master’s degree.
Autonomy, enthusiasm for new technologies, rigor and teamwork are your essential qualities.
You can easily write technical documentation and user manuals.
FPGA TRAINEE SKILLS
The skills of the FPGA trainee that will be reinforced/transmitted includes:
- Design in VHDL language
- Writing documents on the whole V cycle
- RTL coding and VHDL test-benching
- Simulation with Mentor Graphics Modelism
- Physical implementation (synthesis, placement, layout, timing analysis)
- Validation on evaluation board
- The creation of scripts in TCL, Perl, etc.
FPGA INTERNSHIP DURATION
It is an end of studies project, so the duration of the internship is about 6 months.
Nevertheless, the assignment can sometimes be carried out as part of a gap year.
FPGA TRAINEE BONUS
The internship is agreed and remunerated.
FPGA TRAINEE IN PARIS, GRENOBLE, NICE AND TOULOUSE
FPGA trainees are welcomed at the ELSYS Design technical centers in Paris, Grenoble, Nice, Grenoble and Toulouse (France).
Offers can be consulted on our job site, generally from October.
If no offer is online at the time of your consultation, do not hesitate to submit a spontaneous application, it will be systematically studied.