ELSYS Design Joins the Cadence Connections Verification Program

ELSYS Design Joins the Cadence Connections Verification Program

The international design house joins Cadence Connections Verification Program to accelerate the adoption of new technologies and improve verification productivity.

ELSYS Design has been collaborating with semiconductor companies for many years and expands its recognition by joining the Cadence program (discover our digital design verification services).

ELSYS Design supports clients interested in implementing Cadence verification solutions from its own network of design centers located in Western Europe, Eastern Europe and the USA. Press release.

Paris, March 21st, 2023 – ELSYS Design, a leading international semiconductor and electronic systems design house, announces it has joined the Cadence® Connections® Verification Program.

ELSYS Design provides hardware and software expert design and verification services and supports companies all along their embedded system developments. In the verification domain, ELSYS Design brings its proven experience to the table and helps companies with the definition and set-up of verification flows, the development of verification intellectual property (VIP), and the execution of verification projects. ELSYS Design provides expertise in all the areas of verification, which includes SV-UVM, and can support complete clients’ projects or focus its work on dedicated IPs.

The Cadence Connections Verification Program brings together a worldwide network of services, training, and IP development experts that support Cadence verification solutions. Based on years of experience in re-usable VIP, program members accelerate the adoption of new technologies and improve verification team productivity.

By joining the Cadence program, ELSYS can provide customers with the following benefits:

  • Readily available expert assistance for the implementation of Cadence verification solutions and the Accellera Universal Verification Methodology (UVM).
  • Shared knowledge base built upon years of experience with many different types of development teams and products.

“Verification today represents 70% to 80% of the effort in a chip design project,” says Pascal Barioulet, the ELSYS Design Business Director. “We have talented France and Serbia based verification teams with extensive experience in IP, sub-system and chip-level verification projects, across a large range of application areas and are fully committed to supporting worldwide clients in their design and verification projects. Our strengths combined with tools from Cadence augment our added-value to customers.”

“By joining the Cadence Connections Verification Program, the ELSYS team has taken an extra step to expand its expertise with Cadence verification solutions,” said Pat Dutrow, Marketing Director for EDA Vendor Relations, at Cadence. “We look forward to collaborating with them to enable customer successes across Europe and the US.”